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Jackputer

Ongoing

Solo — nand2tetris computer from NAND gates up

Research

Building a computer from scratch, starting from universal NAND gates, with interactive browser views from high-level chips down to primitive gates.

HDLVerilogPythonSVG
Live site GitHub
Jackputer ALU schematic expanded one level, showing Mux, Not and And subchips wired across 16 bits
ALU chip design, expanded one level into its Mux16, Not16 and And16 subchips
Jackputer chip visualization index
Chip visualizations

Jackputer is my nand2tetris computer. The chips are written in HDL, compiled into structural Verilog, and rendered as interactive browser visualizations. You can explore each design from its high-level blocks down to the primitive NAND gates.

So far it covers logic gates, the arithmetic chips and ALU, and the memory chips and program counter. Each chip can be viewed at its own level or expanded one or two dependency layers deeper.